Turn a proven architectural idea into hardware that computes correctly. You will design the digital logic for a justified accelerator or subsystem.
Not open yet: Custom silicon gate
This work starts when that stage arrives, so there is no application to submit today and we will not pretend otherwise. What is written below is what the role is for and what would make somebody right for it, published early on purpose so you can decide whether it is worth watching.
The work
Develop synthesizable RTL, interfaces, control logic and power-aware behavior. Work with verification, compiler and physical-design engineers from the beginning. Track area, frequency and energy against a documented workload and resist optimizing a benchmark that does not represent the product.
The milestone
In your first 90 days after program activation, deliver a verified block prototype with synthesis results and a traceable specification.
Evidence
Bring digital design fundamentals, SystemVerilog or equivalent RTL experience, and strong reasoning about pipelines, resets, clock domains and backpressure.
Evidence, not credentials. We are describing work you can point at, in whatever form it exists.
The exercise
Review a small streaming datapath for correctness under stalls, reset and malformed input before discussing throughput.