Make an approved chip design manufacturable and reliable at its intended operating limits. You will connect logical intent to physical implementation.
Not open yet: Custom silicon gate
This work starts when that stage arrives, so there is no application to submit today and we will not pretend otherwise. What is written below is what the role is for and what would make somebody right for it, published early on purpose so you can decide whether it is worth watching.
The work
Own floorplanning, placement, routing, clock trees, timing closure and power-integrity coordination. Work with foundry and implementation partners on design rules and signoff. Report performance, power and area together with corner assumptions and remaining risks.
The milestone
In your first 90 days after program activation, deliver an implementation feasibility study and a credible closure plan for the selected block.
Evidence
Bring hands-on physical design and static-timing analysis experience. Understand process-voltage-temperature corners, signal integrity and the cost of late architectural changes.
Evidence, not credentials. We are describing work you can point at, in whatever form it exists.
The exercise
Explain a timing failure that cannot be solved by simply increasing cell size, and compare the available architectural fixes.