Make sure every shipped chip behaves correctly beyond the simulator. You will connect design-for-test, bring-up and production learning.
Not open yet: Custom silicon gate
This work starts when that stage arrives, so there is no application to submit today and we will not pretend otherwise. What is written below is what the role is for and what would make somebody right for it, published early on purpose so you can decide whether it is worth watching.
The work
Plan scan, memory self-test and manufacturing test coverage with design partners. Develop board-level bring-up and characterization across operating conditions. Correlate failures with design evidence, track yield and distinguish silicon defects from firmware or board problems.
The milestone
In your first 90 days after program activation, deliver a bring-up plan, test fixtures specification and a traceable failure-triage workflow.
Evidence
Bring experience in DFT, post-silicon validation or product engineering. Show disciplined measurement, reproducible lab work and careful handling of incomplete evidence.
Evidence, not credentials. We are describing work you can point at, in whatever form it exists.
The exercise
Investigate a failure that appears only after warm restart at a particular voltage and describe how you would isolate its cause.